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FACULTY OF ELECTRICAL &
ELECTRONICS ENGINEERING

Abstract:

As the complexity of digital system increase drastically from time to time, debugging a digital system has become a challenging task. Usually, defects detection in most digital design are simulated before it is fabricated. As the scale of the logic designs increased, hardware defects are difficult and time consuming to model in simulation. As the result, the debugging theory of using an in-system embedded logic analyzer was introduced. This paper describes the development of a system-on-chip (SoC) proposed as a low cost and high performance PC-based logic analyzer. It is implemented on an Altera Cyclone II FPGA DE1. Besides, the logic analyzer has 16 independent channels and operates at frequency up to 100MHz. The analyzer is communicates to PC through an RS232 serial communication. This allows user to configure the acquisition parameter and visualize the data through a user-friendly graphical user interface (GUI). A main inspiration for this paper is to attain an efficient and free in-system logic analyzer autonomous from any FPGA platform. It can be used in any FPGA, even the designs of ASICs and SoCs.